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ltm4601a/ltm4601a-1 1 4601afc 12a module regulators with pll, output tracking and margining n telecom and networking equipment n servers n complete switch mode power supply n wide input voltage range: 4.5v to 20v n 12a dc typical, 14a peak output current n 0.6v to 5v output voltage n output voltage tracking and margining n redundant mounting pads for enhanced solder- joint strength n parallel multiple modules for current sharing n differential remote sensing for precision regulation (ltm4601a only) n pll frequency synchronization n 1.5% total dc error n current foldback protection (disabled at start-up) n pb-free rohs compliant package gold finish lga (e4) or sac 305 bga (e1) n ultrafast? transient response n current mode control n up to 95% efficiency at 5v in , 3.3v out n programmable soft-start n output overvoltage protection n enhanced (15mm 15mm 2.82mm) surface mount lga and (15mm 15mm 3.42mm) bga packages 1.5v/12a power supply with 4.5v to 20v input efficiency and power loss vs load current the ltm ? 4601a is a complete 12a step-down switch mode dc/dc power supply with onboard switching controller, mosfets, inductor and all support components. the module ? regulator is housed in a small surface mount 15mm 15mm 2.82mm lga or 15mm 15mm 3.42mm bga package. the ltm4601a lga and bga packages are designed with redundant mounting pads to enhance solder-joint strength for extended temperature cycling endurance. operating over an input voltage range of 4.5v to 20v, the ltm4601a supports an output voltage range of 0.6v to 5v as well as output voltage tracking and margining. the high efficiency design delivers 12a continuous current (14a peak). only bulk input and output capacitors are needed to complete the design. the low profile and light weight package easily mounts on the back side of pc boards. the module regulator can be synchronized with an external clock for reducing undesirable frequency harmonics and allows polyphase ? operation for high load currents. an onboard differential remote sense amplifier can be used to accurately regulate an output voltage independent of load current. the onboard remote sense amplifier is not available in the ltm4601a-1. l , lt, ltc, ltm, module and polyphase are registered trademarks of linear technology corporation. ultrafast and ltpowercad are trademarks of linear technology corporation. all other trademarks are the property of their respective owners. protected by u.s. patents including 5481178, 5847554, 6304066, 6476589, 6580258, 6677210, 6774611. typical a pplica t ion fea t ures a pplica t ions descrip t ion v out v fb marg0 marg1 v out_lcl diffv out v osns + v osns ? pgood run comp intv cc drv cc mpgm track/ss pllin ltm4601a on/off r1 392k r set 40.2k margin control c out 4601a ta01a v out 1.5v 12a clock sync track/ss control 100pf c in v in f set pgnd sgnd 5% margin v in 4.5v to 20v load current (a) 0 50 efficiency (%) power loss (w) 55 65 70 75 95 4601a ta01b 60 2 4 6 8 10 12 14 80 85 90 0.5 1.0 2.0 4.0 1.5 2.5 3.0 3.5 12v in 12v in 5v in 5v in efficiency power loss
ltm4601a/ltm4601a-1 2 4601afc intv cc , drv cc , v out_lcl , v out (v out 3.3v with diffv out ) .................................................... C 0 .3v to 6v pllin, track/ss, mpgm, marg0, marg1, pgood, f set .............................. C 0 .3v to intv cc + 0.3v run ............................................................. C 0.3v to 5v v fb , comp ................................................ C 0 .3v to 2.7 v (note 1) lead free finish tray part marking* package description temperature range (note 2) ltm4601aev#pbf ltm4601aev#pbf ltm4601av 133-lead (15mm 15mm 2.82mm) lga C40c to 85c ltm4601aiv#pbf ltm4601aiv#pbf ltm4601av 133-lead (15mm 15mm 2.82mm) lga C40c to 85c ltm4601aev-1#pbf ltm4601aev-1#pbf ltm4601av-1 133-lead (15mm 15mm 2.82mm) lga C40c to 85c ltm4601aiv-1#pbf ltm4601aiv-1#pbf ltm4601av-1 133-lead (15mm 15mm 2.82mm) lga C40c to 85c ltm4601aey#pbf ltm4601aey#pbf ltm4601ay 133-lead (15mm 15mm 3.42mm) bga C40c to 85c ltm4601aiy#pbf ltm4601aiy#pbf ltm4601ay 133-lead (15mm 15mm 3.42mm) bga C40c to 85c consult ltc marketing for parts specified with wider operating temperature ranges. *the temperature grade is identified by a label on the shipping container. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ this product is only offered in trays. for more information go to: http://www.linear.com/packaging/ a bsolu t e maxi m u m r a t ings or d er in f or m a t ion (see table 5. pin assignment) v in ............................................................. C 0 .3v to 20v v osns + , v osns C .......................... C 0 .3v to intv cc + 0.3v operating temperature range (note 2).... C40c to 85c junction temperature ........................................... 1 25c storage temperature range .................. C 55c to 125c bga package 133-lead (15mm 15mm 3.42mm) top view v in pgnd v out v osns + v osns ? diffv out v out_lcl sgnd f set marg0 marg1 drv cc intv cc v fb pgood intv cc pllin track/ss run comp mpgm mtp1 mtp2 mtp3 t jmax = 125c, ja = 15.5c/w, jcbottom = 6.5c/w ja derived from 95mm 76mm pcb with 4 layers weight = 1.9g v in pgnd v out v osns + /nc2* v osns ? /nc1* diffv out /nc3* v out_lcl sgnd f set marg0 marg1 drv cc intv cc v fb pgood intv cc pllin track/ss run comp mpgm lga package 133-lead (15mm 15mm 2.82mm) top view mtp1 mtp2 mtp3 t jmax = 125c, ja = 15c/w, jc = 6c/w ja derived from 95mm 76mm pcb with 4 layers weight = 1.7g *ltm4601a-1 only p in c on f igura t ion
ltm4601a/ltm4601a-1 3 4601afc symbol parameter conditions min typ max units v in(dc) input dc voltage l 4.5 20 v v out(dc) output voltage, total variation with line and load c in = 10f 3, c out = 200f, r set = 40.2k v in = 5v to 20v, i out = 0a to 12a (note 5) l 1.478 1.5 1.522 v input specifications v in(uvlo) undervoltage lockout threshold i out = 0a 3.2 4 v i inrush(vin) input inrush current at startup i out = 0a. v out = 1.5v v in = 5v v in = 12v 0.6 0.7 a a i q(vin,noload) input supply bias current v in = 12v, no switching v in = 12v, v out = 1.5v, switching continuous v in = 5v, no switching v in = 5v, v out = 1.5v, switching continuous shutdown, run = 0, v in = 12v 3.8 38 2.5 42 22 ma ma ma ma a i s(vin) input supply current v in = 12v, v out = 1.5v, i out = 12a v in = 12v, v out = 3.3v, i out = 12a v in = 5v, v out = 1.5v, i out = 12a 1.81 3.63 4.29 a a a intv cc v in = 12v, run > 2v no load 4.7 5 5.3 v output specifications i outdc output continuous current range v in = 12v, v out = 1.5v (note 5) 0 12 a ?v out(line) v out line regulation accuracy v out = 1.5v, i out = 0a, v in from 4.5v to 20v l 0.3 % ?v out(load) v out load regulation accuracy v out = 1.5v, 0a to 12a (note 5) v in = 12v, with remote sense amplifier v in = 12v (ltm4601a-1) l l 0.25 1 % % v out(ac) output ripple voltage i out = 0a, c out = 2 100f x5r ceramic v in = 12v, v out = 1.5v v in = 5v, v out = 1.5v 20 18 mv p-p mv p-p f s output ripple voltage frequency i out = 5a , v in = 12v, v out = 1.5v 850 khz ?v out(start) turn-on overshoot c out = 200f, v out = 1.5v, i out = 0a, track/ss = 10nf v in = 12v v in = 5v 20 20 mv mv t start turn-on time c out = 200f, v out = 1.5v, track/ss = open, i out = 1a resistive load v in = 12v v in = 5v 0.5 0.5 ms ms v outls peak deviation for dynamic load load: 0% to 50% to 0% of full load, c out = 2 22f ceramic, 470f 4v sanyo poscap v in = 12v v in = 5v 35 35 mv mv t settle settling time for dynamic load step load: 0% to 50%, or 50% to 0% of full load v in = 12v 25 s i outpk output current limit c out = 200f ceramic v in = 12v, v out = 1.5v v in = 5v, v out = 1.5v 17 17 a a the l denotes the specifications which apply over the specified operating temperature range (note 2), otherwise specifications are at t a = 25c, v in = 12v, per typical application (front page) configuration. e lec t rical c harac t eris t ics
ltm4601a/ltm4601a-1 4 4601afc symbol parameter conditions min typ max units remote sense amp (note 3) (ltm4601a only, not supported in the ltm4601a-1) v osns + , v osns C cm range common mode input voltage range v in = 12v, run > 2v 0 intv cc C 1 v diffv out range output voltage range v in = 12v, diffv out load = 100k 0 intv cc C 1 v v os input offset voltage magnitude 1.25 mv a v differential gain 1 v/v gbp gain-bandwidth product 3 mhz sr slew rate 2 v/s r in input resistance v osns + to gnd 20 k cmrr common mode rejection mode 100 db control stage v fb error amplifier input voltage accuracy i out = 0a, v out = 1.5v l 0.594 0.6 0.606 v v run run pin on/off threshold 1 1.5 1.9 v i track/ss soft-start charging current v track/ss = 0v C1 C1.5 C2 a t on(min) minimum on-time (note 4) 50 100 ns t off(min) minimum off-time (note 4) 250 400 ns r pllin pllin input resistance 50 k i drvcc current into drv cc pin v out = 1.5v, i out = 1a, drv cc = 5v 18 25 ma r fbhi resistor between v out_lcl and v fb 60.098 60.4 60.702 k v mpgm margin reference voltage 1.18 v v marg0 , v marg1 marg0, marg1 voltage thresholds 1.4 v pgood output ?v fbh pgood upper threshold v fb rising 7 10 13 % ?v fbl pgood lower threshold v fb falling C7 C10 C13 % ?v fb(hys) pgood hysteresis v fb returning 1.5 % v pgl pgood low voltage i pgood = 5ma 0.15 0.4 v the l denotes the specifications which apply over the specified operating temperature range (note 2), otherwise specifications are at t a = 25c, v in = 12v, per typical application (front page) configuration. note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: the ltm4601a is tested under pulsed load conditions such that t j t a . the ltm4601ae/ltm4601ae-1 are guaranteed to meet performance specifications from 0c to 85c. specifications over the C 40c to 85c operating temperature range are assured by design, characterization and correlation with statistical process controls. the ltm4601ai/ltm4601ai-1 are guaranteed over the C 40c to 85c operating temperature range. note 3: remote sense amplifier recommended for 3.3v output. note 4: 100% tested at wafer level only. note 5: see output current derating curves for different v in , v out and t a . elec t rical c harac t eris t ics
ltm4601a/ltm4601a-1 5 4601afc efficiency vs load current with 5v in efficiency vs load current with 12v in efficiency vs load current with 20v in 1.2v transient response 1.5v transient response 2.5v transient response 3.3v transient response (see figure 18 for all curves) 1.8v transient response typical p er f or m ance c harac t eris t ics load current (a) 0 efficiency (%) 75 80 85 15 4601a g01 70 65 60 55 50 5 10 90 95 100 0.6v out 1.2v out 1.5v out 2.5v out 3.3v out load current (a) 0 50 efficiency (%) 55 65 70 75 100 85 5 10 4601a g02 60 90 95 80 15 0.6v out 1.2v out 1.5v out 2.5v out 3.3v out 5v out load current (a) 0 100 90 95 85 80 75 70 65 60 55 50 4601a g03 5 10 15 efficiency (%) 1.2v out 1.5v out 2.5v out 3.3v out 5.0v out v out 50mv/div 20s/div 4601a g04 i out 5a/div 1.2v at 6a/s load step c out = 3 ? 22f 6.3v ceramics, 470f 4v sanyo poscap c3 = 100pf v out 50mv/div 20s/div 4601a g05 i out 5a/div 1.5v at 6a/s load step c out = 3 ? 22f 6.3v ceramics, 470f 4v sanyo poscap c3 = 100pf v out 50mv/div 20s/div 4601a g06 i out 5a/div 1.8v at 6a/s load step c out = 3 ? 22f 6.3v ceramics, 470f 4v sanyo poscap c3 = 100pf v out 50mv/div 20s/div 4601a g07 i out 5a/div 2.5v at 6a/s load step c out = 3 ? 22f 6.3v ceramics, 470f 4v sanyo poscap c3 = 100pf v out 50mv/div 20s/div 4601a g08 i out 5a/div 3.3v at 6a/s load step c out = 3 ? 22f 6.3v ceramics, 470f 4v sanyo poscap c3 = 100pf
ltm4601a/ltm4601a-1 6 4601afc (see figure 18 for all curves) start-up, i out = 12a (resistive load) start-up, i out = 0a v in to v out step-down ratio short-circuit protection, i out = 0a short-circuit protection, i out = 12a track, i out = 12a typical p er f or m ance c harac t eris t ics input voltage (v) 0 output voltage (v) 3.0 4.0 5.5 5.0 16 4601a g11 2.0 1.0 2.5 3.5 4.5 1.5 0.5 0 42 86 12 14 18 10 20 3.3v output with 130k added from v out to f set 5v output with 100k resistor added from f set to gnd 5v output with no resistor added from f set to gnd 2.5v output 1.8v output 1.5v output 1.2v output v out 0.5v/div 5ms/div 4601a g09 i in 0.5a/div v in = 12v v out = 1.5v c out = 470f, 3 22f soft-start = 10nf v out 0.5v/div 2ms/div 4601a g10 i in 1a/div v in = 12v v out = 1.5v c out = 470f, 3 22f soft-start = 10nf v fb 0.5v/div track/ss 0.5v/div 2ms/div 4601a g12 v out 1v/div v in = 12v v out = 1.5v c out = 470f, 3 22f soft-start = 10nf v out 0.5v/div 50s/div 4601a g13 i in 1a/div v in = 12v v out = 1.5v c out = 470f, 3 22f soft-start = 10nf v out 0.5v/div 50s/div 4601a g14 i in 1a/div v in = 12v v out = 1.5v c out = 470f, 3 22f soft-start = 10nf
ltm4601a/ltm4601a-1 7 4601afc (see package description for pin assignment) v in (bank 1): power input pins. apply input voltage be- tween these pins and pgnd pins. recommend placing input decoupling capacitance directly between v in pins and pgnd pins. v out (bank 3): power output pins. apply output load between these pins and pgnd pins. recommend placing output decoupling capacitance directly between these pins and pgnd pins. see figure 15. pgnd (bank 2): power ground pins for both input and output returns. v osns C (pin m12): (C) input to the remote sense ampli- fier. this pin connects to the ground remote sense point. the remote sense amplifier is used for v out 3.3v. tie to intv cc if not used. nc1 (pin m12): no internal connection on the ltm4601a-1. v osns + (pin j12): (+) input to the remote sense ampli- fier. this pin connects to the output remote sense point. the remote sense amplifier is used for v out 3.3v. tie to gnd if not used. nc2 (pin j12): no internal connection on the ltm4601a-1. diffv out (pin k12): output of the remote sense ampli- fier. this pin connects to the v out_lcl pin. leave floating if not used. nc3 (pin k12): no internal connection on the ltm4601a-1. drv cc (pin e12): this pin normally connects to intv cc for powering the internal mosfet drivers. this pin can be biased up to 6v from an external supply with about 50ma capability, or an external circuit shown in figure 16. this improves efficiency at the higher input voltages by reducing power dissipation in the module. intv cc (pin a7, d9): this pin is for additional decoupling of the 5v internal regulator. these pins are internally connected. pin a7 is a test pin. pllin (pin a8): external clock synchronization input to the phase detector. this pin is internally terminated to sgnd with a 50k resistor. apply a clock with high level above 2v and below intv cc . see the applications infor - mation section. track/ss (pin a9): output voltage tracking and soft- start pin. when the module is configured as a master output, then a soft-start capacitor is placed on this pin to ground to control the master ramp rate. a soft-start capacitor can be used for soft-start turn on as a stand alone regulator. slave operation is performed by putting a resistor divider from the master output to ground, and connecting the center point of the divider to this pin. see the applications information section. mpgm (pins a12, b11): programmable margining input. a resistor from this pin to ground sets a current that is equal to 1.18v/r. this current multiplied by 10k will equal a value in millivolts that is a percentage of the 0.6v reference voltage. see the applications information sec- tion. to parallel ltm4601as, each requires an individual mpgm resistor. do not tie mpgm pins together. both pins are internally connected. pin a12 is a test pin. f set (pins b12, c11): frequency set internally to 850khz. an external resistor can be placed from this pin to ground to increase frequency. see the applications information section for frequency adjustment. both pins are internally connected. pin b12 is a test pin. v fb (pin f12): the negative input of the error amplifier. internally, this pin is connected to v out_lcl pin with a 60.4k precision resistor. different output voltages can be programmed with an additional resistor between v fb and sgnd pins. see the applications information section. marg0 (pin c12): this pin is the lsb logic input for the margining function. together with the marg1 pin it will determine if margin high, margin low or no margin state is applied. the pin has an internal pull-down resistor of 50k. see the applications information section. p in func t ions
ltm4601a/ltm4601a-1 8 4601afc marg1 (pin d12): this pin is the msb logic input for the margining function. together with the marg0 pin it will determine if margin high, margin low or no margin state is applied. the pin has an internal pull-down resistor of 50k. see the applications information section. sgnd (pins h12, h11, g11): signal ground. these pins connect to pgnd at output capacitor point. see figure 15. comp (pin a11): current control threshold and error amplifier compensation point. the current comparator threshold increases with this control voltage. the voltage ranges from 0v to 2.4v with 0.7v corresponding to zero sense voltage (zero current). pgood (pins g12, f11): output voltage power good indicator. open-drain logic output that is pulled to ground when the output voltage is not within 10% of the regula- tion point, after a 25s power bad mask timer expires. run (pin a10): run control pin. a voltage above 1.9v will turn on the module, and when below 1v, will turn off the module. a programmable uvlo function can be accomplished by connecting to a resistor divider from v in to ground. see figure 1. this pin has a 5.1v zener to ground. maximum pin voltage is 5v. limit current into the run pin to less than 1ma. v out_lcl (pin l12): v out connects directly to this pin to bypass the remote sense amplifier, or diffv out con - nects to this pin when the remote sense amplifier is used. v out_lcl can be connected to v out on the ltm4601a-1, v out is internally connected to v out_lcl with 50 in the ltm4601a-1. mtp1, mtp2, mpt3 (pins c10, d10, d11 ): extra mount- ing pads. these pads must be left floating (electrical open circuit) and are used for enhanced solder joint strength. (see package description for pin assignment) p in func t ions
ltm4601a/ltm4601a-1 9 4601afc figure 1. simplified ltm4601a/ltm4601a-1 block diagram s i m pli f ie d b lock diagra m + internal comp sgnd comp pgood run v out_lcl v in >1.9v = on <1v = off max = 5v marg1 marg0 mpgm pllin c ss intv cc drv cc track/ss v fb f set 50k 39.2k r set 40.2k 50k 60.4k v out 1m (50, ltm4601a-1) 5.1v zener power control q1 v in 4.5v to 20v v out 1.5v 12a q2 10k 10k 10k not included in the ltm4601a-1 v osns ? = nc1 v osns + = nc2 diffv out = nc3 50k 10k intv cc + ? 22f 1.5f 0.47h c in + c out pgnd v osns ? v osns + diffv out 4601a f01 4.7f r1 r2 uvlo function symbol parameter conditions min typ max units c in external input capacitor requirement (v in = 4.5v to 20v, v out = 1.5v) i out = 12a 20 30 f c out external output capacitor requirement (v in = 4.5v to 20v, v out = 1.5v) i out = 12a 100 200 f t a = 25c, v in = 12v. use figure 1 configuration. decoupling r equire m en t s
ltm4601a/ltm4601a-1 10 4601afc power module description the ltm4601a is a standalone nonisolated switching mode dc/dc power supply. it can deliver up to 12a of dc output current with few external input and output capacitors. this module provides precisely regulated output voltage programmable via one external resistor from 0.6v dc to 5.0v dc over a 4.5v to 20v wide input voltage. the typical application schematic is shown in figure 18. the ltm4601a has an integrated constant on-time current mode regulator, ultralow r ds(on) fets with fast switch - ing speed and integrated schottky diodes. the typical switching frequency is 850khz at full load. with current mode control and internal feedback loop compensation, the ltm4601a module has sufficient stability margins and good transient performance under a wide range of operat - ing conditions and with a wide range of output capacitors, even all ceramic output capacitors. current mode control provides cycle-by-cycle fast current limit. besides, foldback current limiting is provided in an overcurrent condition while v fb drops. internal overvolt - age and undervoltage comparators pull the open-drain pgood output low if the output feedback voltage exits a 10% window around the regulation point. furthermore, in an overvoltage condition, internal top fet q1 is turned off and bottom fet q2 is turned on and held on until the overvoltage condition clears. pulling the run pin below 1v forces the controller into its shutdown state, turning off both q1 and q2. at low load current, the module works in continuous current mode by default to achieve minimum output ripple voltage. when drv cc pin is connected to intv cc an integrated 5v linear regulator powers the internal gate drivers. if a 5v external bias supply is applied on the drv cc pin, then an efficiency improvement will occur due to the reduced power loss in the internal linear regulator. this is especially true at the high end of the input voltage range. the ltm4601a has a very accurate differential remote sense amplifier with very low offset. this provides for very accurate output voltage measurement at the load. the mpgm pin, marg0 pin and marg1 pin are used to support voltage margining, where the percentage of margin is programmed by the mpgm pin, and the marg0 and marg1 select margining. the pllin pin provides frequency synchronization of the device to an external clock. the track/ss pin is used for power supply tracking and soft-start programming. o pera t ion
ltm4601a/ltm4601a-1 11 4601afc the typical ltm4601a application circuit is shown in figure 18. external component selection is primarily determined by the maximum load current and output voltage. refer to table 2 for specific external capacitor requirements for a particular application. v in to v out step-down ratios there are restrictions in the maximum v in and v out step down ratio that can be achieved for a given input voltage. these constraints are shown in the typical performance characteristics curves labeled v in to v out step-down ratio. note that additional thermal derating may apply. see the thermal considerations and output current derating section of this data sheet. output voltage programming and margining the pwm controller has an internal 0.6v reference voltage. as shown in the block diagram, a 1m and a 60.4k 0.5% internal feedback resistor connects v out and v fb pins together. the v out_lcl pin is connected between the 1m and the 60.4k resistor. the 1m resistor is used to protect against an output overvoltage condition if the v out_lcl pin is not connected to the output, or if the remote sense amplifier output is not connected to v out_lcl . in these cases, the output voltage will default to 0.6v. adding a resistor r set from the v fb pin to sgnd pin programs the output voltage: v out = 0.6v 60.4k + r set r set table 1. r set standard 1% resistor values vs v out r set (k) open 60.4 40.2 30.1 25.5 19.1 13.3 8.25 v out (v) 0.6 1.2 1.5 1.8 2 2.5 3.3 5 the mpgm pin programs a current that when multiplied by an internal 10k resistor sets up the 0.6v reference offset for margining. a 1.18v reference divided by the r pgm resistor on the mpgm pin programs the current. calculate v out(margin) : v out(margin) = %v out 100 ? v out where %v out is the percentage of v out you want to margin, and v out(margin) is the margin quantity in volts: r pgm = v out 0.6v ? 1.18v v out(margin) ? 10k where r pgm is the resistor value to place on the mpgm pin to ground. the margining voltage, v out(margin) , will be added or subtracted from the nominal output voltage as determined by the state of the marg0 and marg1 pins. see the truth table below: marg1 marg0 mode low low no margin low high margin up high low margin down high high no margin input capacitors ltm4601a module should be connected to a low ac impedance dc source. input capacitors are required to be placed adjacent to the module. in figure 18, the 10f ceramic input capacitors are selected for their ability to handle the large rms current into the converter. an input bulk capacitor of 100f is optional. this 100f capacitor is only needed if the input source impedance is compro - mised by long inductive leads or traces. a pplica t ions i n f or m a t ion
ltm4601a/ltm4601a-1 12 4601afc for a buck converter, the switching duty cycle can be estimated as: d = v out v in without considering the inductor ripple current, the rms current of the input capacitor can be estimated as: i cin(rms) = i out(max) % ? d ? 1C d ( ) in the above equation, % is the estimated efficiency of the power module. c in can be a switcher-rated electrolytic aluminum capacitor, os-con capacitor or high value ce - ramic capacitor. note the capacitor ripple current ratings are often based on temperature and hours of life. this makes it advisable to properly derate the input capacitor, or choose a capacitor rated at a higher temperature than required. always contact the capacitor manufacturer for derating requirements. in figure 18, the 10f ceramic capacitors are together used as a high frequency input decoupling capacitor. in a typical 12a output application, three very low esr, x5r or x7r 10f ceramic capacitors are recommended. these decoupling capacitors should be placed directly adjacent to the module input pins in the pcb layout to minimize the trace inductance and high frequency ac noise. each 10f ceramic is typically good for 2a to 3a of rms ripple current. refer to your ceramics capacitor catalog for the rms current ratings. multiphase operation with multiple ltm4601a devices in parallel will lower the effective input rms ripple current due to the interleaving operation of the regulators. application note 77 provides a detailed explanation. refer to figure 2 for the input capacitor ripple current reduction as a func - tion of the number of phases. the figure provides a ratio of rms ripple current to dc load current as function of duty cycle and the number of paralleled phases. pick the corresponding duty cycle and the number of phases to arrive at the correct ripple current value. for example, the 2-phase parallel ltm4601a design provides 24a at 2.5v output from a 12v input. the duty cycle is dc = 2.5v/12v = 0.21. the 2-phase curve has a ratio of ~0.25 for a duty cycle of 0.21. this 0.25 ratio of rms ripple current to a dc load current of 24a equals ~6a of input rms ripple current for the external input capacitors. output capacitors the ltm4601a is designed for low output ripple voltage. the bulk output capacitors defined as c out are chosen with low enough effective series resistance (esr) to meet the output ripple voltage and transient requirements. c out can be a low esr tantalum capacitor, a low esr polymer capacitor or a ceramic capacitor. the typical capacitance is 200f if all ceramic output capacitors are used. additional output filtering may be required by the system designer if further reduction of output ripple or dynamic transient spikes is required. table 2 shows a matrix of different output voltages and output capacitors to minimize the voltage droop and overshoot during a 5a/s transient. the table optimizes total equivalent esr and total bulk capacitance to maximize transient performance. figure 2. normalized input rms ripple current vs duty cycle for one to six modules (phases) a pplica t ions i n f or m a t ion duty cycle (v out /v in ) 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 0.6 0.5 0.4 0.3 0.2 0.1 0 4601a f02 rms input ripple current dc load current 6-phase 4-phase 12-phase 3-phase 2-phase 1-phase
ltm4601a/ltm4601a-1 13 4601afc multiphase operation with multiple ltm4601a devices in parallel will lower the effective output ripple current due to the interleaving operation of the regulators. for example, each ltm4601as inductor current in a 12v to 2.5v multiphase design can be read from the inductor ripple current vs duty cycle graph (figure 3). the large ripple current at low duty cycle and high output voltage can be reduced by adding an external resistor from f set to ground which increases the frequency. if the duty cycle is dc = 2.5v/12v = 0.21, the inductor ripple current for 2.5v output at 21% duty cycle is ~6a in figure 3. figure 4 provides a ratio of peak-to-peak output ripple cur - rent to the inductor current as a function of duty cycle and the number of paralleled phases. pick the corresponding duty cycle and the number of phases to arrive at the correct output ripple current ratio value. if a 2-phase operation is chosen at a duty cycle of 21%, then 0.6 is the ratio. this 0.6 ratio of output ripple current to inductor ripple of 6a equals 3.6a of effective output ripple current. refer to application note 77 for a detailed explanation of output ripple current reduction as a function of paralleled phases. figure 4. normalized output ripple current vs duty cycle, dlr = v o t/l i , dlr = each phases inductor current figure 3. inductor ripple current vs duty cycle applica t ions in f or m a t ion duty cycle (v o /v in ) 0.1 0.15 0.2 0.25 0.350.3 0.4 0.45 0.5 0.55 0.6 0.65 0.7 0.75 0.8 0.85 0.9 1.00 0.95 0.90 0.85 0.80 0.75 0.70 0.65 0.60 0.55 0.50 0.45 0.40 0.35 0.30 0.25 0.20 0.15 0.10 0.05 0 4601a f04 6-phase 4-phase 3-phase 2-phase 1-phase peak-to-peak output ripple current dir ratio = duty cycle (v out /v in ) 0 0 i l (a) 2 4 6 8 10 12 0.2 0.4 0.6 0.8 4601a f03 2.5v output 5v output 1.8v output 1.5v output 1.2v output 3.3v output with 130k added from v out to f set 5v output with 100k added from f set to gnd
ltm4601a/ltm4601a-1 14 4601afc the output ripple voltage has two components that are related to the amount of bulk capacitance and effective series resistance (esr) of the output bulk capacitance. therefore, the output ripple voltage can be calculated with the known effective output ripple current. the equation: ?v out(p-p) (?i l /(8 ? f ? m ? c out ) + esr ? ?i l ), where f is frequency and m is the number of parallel phases. this calculation process can be easily accomplished by using ltpowercad?. fault conditions: current limit and overcurrent foldback ltm4601a has a current mode controller, which inher - ently limits the cycle-by-cycle inductor current not only in steady-state operation, but also in response to transients. to further limit current in the event of an overload condition, the ltm4601a provides foldback current limiting. if the output voltage falls by more than 50%, then the maximum output current is progressively lowered to about one sixth of its full current limit value. soft-start and tracking the track/ss pin provides a means to either soft-start the regulator or track it to a different power supply. a capacitor on this pin will program the ramp rate of the output voltage. a 1.5a current source will charge up the external soft-start capacitor to 80% of the 0.6v internal voltage reference plus or minus any margin delta. this will control the ramp of the internal reference and the output voltage. the total soft-start time can be calculated as: t softstart = 0.8 ? 0.6v v out(margin) ( ) ? c ss 1.5a when the run pin falls below 1.5v, then the track/ss pin is reset to allow for proper soft-start control when the regulator is enabled again. current foldback and forced continuous mode are disabled during the soft-start pro- cess. the soft-start function can also be used to control the output ramp up time, so that another regulator can be easily tracked to it. output voltage tracking output voltage tracking can be programmed externally using the track/ss pin. the output can be tracked up and down with another regulator. the master regulators output is divided down with an external resistor divider that is the same as the slave regulators feedback divider. figure 5 shows an example of coincident tracking. ratiometric modes of tracking can be achieved by selecting different resistor values to change the output tracking ratio. the master output must be greater than the slave output for the tracking to work. figure 6 shows the coincident output tracking characteristics. figure 5. coincident tracking schematic figure 6. coincident output tracking characteristics a pplica t ions i n f or m a t ion output voltage time 4601a f06 master output slave output v out v fb marg0 marg1 v out_lcl diffv out v osns + v osns ? pgood mpgm run comp intv cc drv cc track/ss track control pllin ltm4601a r set 40.2k 100k r b 40.2k master output r t 60.4k c out slave output 4601a f05 c in v in f set pgnd sgnd v in
ltm4601a/ltm4601a-1 15 4601afc run enable the run pin is used to enable the power module. the pin has an internal 5.1v zener to ground. the pin can be driven with a logic input not to exceed 5v. the run pin can also be used as an undervoltage lockout (uvlo) function by connecting a resistor divider from the input supply to the run pin: v uvlo = r1 + r2 r2 ? 1.5v see figure 1, simplified block diagram. power good the pgood pin is an open-drain pin that can be used to monitor valid output voltage regulation. this pin monitors a 10% window around the regulation point and tracks with margining. comp pin this pin is the external compensation pin. the module has already been internally compensated for most output voltages. table 2 is provided for most application require - ments. ltpowercad is available for other control loop optimization. pllin the power module has a phase-locked loop comprised of an internal voltage controlled oscillator and a phase detector. this allows the internal top mosfet turn-on to be locked to the rising edge of an external clock. the frequency range is 30% around the operating frequency of 850khz. a pulse detection circuit is used to detect a clock on the pllin pin to turn on the phase-locked loop. the pulse width of the clock has to be at least 400ns and the amplitude at least 2v. the pllin pin must be driven from a low impedance source such as a logic gate located close to the pin. during startup of the regulator, the phase- locked loop function is disabled. intv cc and drv cc connection an internal low dropout regulator produces an internal 5v supply that powers the control circuitry and drv cc for driving the internal power mosfets. therefore, if the system does not have a 5v power rail, the ltm4601a can be directly powered by v in . the gate drive current through the ldo is about 20ma. the internal ldo power dissipation can be calculated as: p ldo_loss = 20ma ? (v in C 5v) the ltm4601a also provides the external gate drive voltage pin drv cc . if there is a 5v rail in the system, it is recom- mended to connect the drv cc pin to the external 5v rail. this is especially true for higher input voltages. do not apply more than 6v to the drv cc pin. a 5v output can be used to power the drv cc pin with an external circuit as shown in figure 16. parallel operation of the module the ltm4601a device is an inherently current mode controlled device. parallel modules will have very good current sharing. this will balance the thermals on the de- sign. figure 19 shows the schematic of a parallel design. the voltage feedback equation changes with the variable n as modules are paralleled: v out = 0.6v 60.4k n + r set r set n is the number of paralleled modules. figure 19 shows an ltm4601a and an ltm4601a-1 used in a parallel design. the 2nd ltm4601a device does not require the remote sense amplifier, therefore, the ltm4601a-1 device is used. an ltm4601a device can be used without the diff amp. v osns + can be tied to ground and the v osns C can be tied to intv cc . diffv out can float. when using multiple ltm4601a-1 devices in parallel with an ltm4601a, limit the number to five for a total of six modules in parallel. applica t ions in f or m a t ion
ltm4601a/ltm4601a-1 16 4601afc figure 7. 1.5v power loss figure 8. 3.3v power loss figure 9. no heat sink 5v in figure 10. bga heat sink 5v in a pplica t ions i n f or m a t ion ambient temperature ( c) 50 0 maximum load current (a) 2 4 6 8 10 12 60 70 80 90 4601a f09 100 5v in , 1.5v out 0lfm 5v in , 1.5v out 200lfm 5v in , 1.5v out 400lfm ambient temperature ( c) 50 0 maximum load current (a) 2 4 6 8 10 12 60 70 80 90 4601a f10 100 5v in , 1.5v out 0lfm 5v in , 1.5v out 200lfm 5v in , 1.5v out 400lfm load current (a) 0 0 power loss (w) 1.0 2.0 3.0 2 4 6 8 4601a f07 10 4.0 5.0 0.5 1.5 2.5 3.5 4.5 12 20v in 12v in 5v in load current (a) 0 0 power loss (w) 1 2 3 4 6 2 4 6 8 4601a f08 10 12 5 20v in 12v in thermal considerations and output current derating the power loss curves in figures 7 and 8 can be used in coordination with the load current derating curves in figures 9 to 14 for calculating an approximate ja for the module with various heat sinking methods. thermal models are derived from several temperature measurements at the bench and thermal modeling analysis. thermal application note 103 provides a detailed explanation of the analysis for the thermal models and the derating curves. tables 3 a nd 4 provide a summary of the equivalent ja for the noted conditions. these equivalent ja parameters are correlated to the measured values, and are improved with air flow. the case temperature is maintained at 100c or below for the derating curves. the maximum case temperature of 100c is to allow for a rise of about 13c to 25c in- side the module regulator with a thermal resistance jc from junction to case between 6c/w to 9c/w. this will maintain the maximum junction temperature inside the module regulator below 125c. safety considerations the ltm4601a modules do not provide isolation from v in to v out . there is no internal fuse. if required, a slow blow fuse with a rating twice the maximum input current needs to be provided to protect each unit from catastrophic failure.
ltm4601a/ltm4601a-1 17 4601afc figure 11. no heat sink 12v in figure 12. bga heat sink 12v in figure 13. 12v in , 3.3v out , no heat sink figure 14. 12v in , 3.3v out , bga heat sink applica t ions in f or m a t ion ambient temperature ( c) 50 0 maximum load current (a) 2 4 6 8 10 12 60 70 80 90 4601a f11 100 12v in , 1.5v out 0lfm 12v in , 1.5v out 200lfm 12v in , 1.5v out 400lfm ambient temperature ( c) 50 0 maximum load current (a) 2 4 6 8 10 12 60 70 80 90 4601a f12 100 12v in , 1.5v out 0lfm 12v in , 1.5v out 200lfm 12v in , 1.5v out 400lfm ambient temperature ( c) 40 0 maximum load current (a) 2 4 6 8 10 12 60 80 4601a f13 100 0lfm 200lfm 400lfm ambient temperature ( c) 40 0 maximum load current (a) 2 4 6 8 10 12 60 80 4601a f14 100 0lfm 200lfm 400lfm
ltm4601a/ltm4601a-1 18 4601afc table 2. output voltage response versus component matrix (refer to figure 18), 0a to 6a load step typical measured values c out1 vendors part number c out2 vendors part number tdk c4532x5r0j107mz (100f, 6.3v) sanyo poscap 6tpe330mil (330f, 6.3v) taiyo yuden jmk432bj107mu-t (100f, 6.3v) sanyo poscap 2r5tpe470m9 (470f, 2.5v) taiyo yuden jmk316bj226ml-t501 (22f, 6.3v) sanyo poscap 4tpe470mcl (470f, 4v) v out (v) c in (ceramic) c in (bulk) c out1 (ceramic) c out2 (bulk) c comp c3 v in (v) droop (mv) peak to peak (mv) recovery time (s) load step (a/s) r set (k) 1.2 2 10f 25v 150f 35v 3 22f 6.3v 470f 4v none 47pf 5 70 140 30 6 60.4 1.2 2 10f 25v 150f 35v 1 100f 6.3v 470f 2.5v none 100pf 5 35 70 20 6 60.4 1.2 2 10f 25v 150f 35v 2 100f 6.3v 330f 6.3v none 22pf 5 70 140 20 6 60.4 1.2 2 10f 25v 150f 35v 4 100f 6.3v none none 100pf 5 40 93 30 6 60.4 1.2 2 10f 25v 150f 35v 3 22f 6.3v 470f 4v none 100pf 12 70 140 30 6 60.4 1.2 2 10f 25v 150f 35v 1 100f 6.3v 470f 2.5v none 100pf 12 35 70 20 6 60.4 1.2 2 10f 25v 150f 35v 2 100f 6.3v 330f 6.3v none 22pf 12 70 140 20 6 60.4 1.2 2 10f 25v 150f 35v 4 100f 6.3v none none 100pf 12 49 98 20 6 60.4 1.5 2 10f 25v 150f 35v 3 22f 6.3v 470f 4v none 100pf 5 48 100 35 6 40.2 1.5 2 10f 25v 150f 35v 1 100f 6.3v 470f 2.5v none 33pf 5 54 109 30 6 40.2 1.5 2 10f 25v 150f 35v 2 100f 6.3v 330f 6.3v none 100pf 5 44 84 30 6 40.2 1.5 2 10f 25v 150f 35v 4 100f 6.3v none none 100pf 5 61 118 30 6 40.2 1.5 2 10f 25v 150f 35v 3 22f 6.3v 470f 4v none 100pf 12 48 100 35 6 40.2 1.5 2 10f 25v 150f 35v 1 100f 6.3v 470f 2.5v none 33pf 12 54 109 30 6 40.2 1.5 2 10f 25v 150f 35v 2 100f 6.3v 330f 6.3v none 100pf 12 44 89 25 6 40.2 1.5 2 10f 25v 150f 35v 4 100f 6.3v none none 100pf 12 54 108 25 6 40.2 1.8 2 10f 25v 150f 35v 3 22f 6.3v 470f 4v none 47pf 5 48 100 30 6 30.1 1.8 2 10f 25v 150f 35v 1 100f 6.3v 470f 2.5v none 100pf 5 44 90 20 6 30.1 1.8 2 10f 25v 150f 35v 2 100f 6.3v 330f 6.3v none 100pf 5 68 140 30 6 30.1 1.8 2 10f 25v 150f 35v 4 100f 6.3v none none 100pf 5 65 130 30 6 30.1 1.8 2 10f 25v 150f 35v 3 22f 6.3v 470f 4v none 100pf 12 60 120 30 6 30.1 1.8 2 10f 25v 150f 35v 1 100f 6.3v 470f 2.5v none 100pf 12 60 120 30 6 30.1 1.8 2 10f 25v 150f 35v 2 100f 6.3v 330f 6.3v none 100pf 12 68 140 30 6 30.1 1.8 2 10f 25v 150f 35v 4 100f 6.3v none none 100pf 12 65 130 20 6 30.1 2.5 2 10f 25v 150f 35v 1 100f 6.3v 470f 4v none 100pf 5 48 103 30 6 19.1 2.5 2 10f 25v 150f 35v 2 100f 6.3v 330f 6.3v none 220pf 5 56 113 30 6 19.1 2.5 2 10f 25v 150f 35v 3 22f 6.3v 470f 4v none none 5 57 116 30 6 19.1 2.5 2 10f 25v 150f 35v 4 100f 6.3v none none 100pf 5 60 115 25 6 19.1 2.5 2 10f 25v 150f 35v 1 100f 6.3v 470f 4v none 100pf 12 48 103 30 6 19.1 2.5 2 10f 25v 150f 35v 3 22f 6.3v 470f 4v none none 12 51 102 30 6 19.1 2.5 2 10f 25v 150f 35v 2 100f 6.3v 330f 6.3v none 220pf 12 56 113 30 6 19.1 2.5 2 10f 25v 150f 35v 4 100f 6.3v none none 220pf 12 70 140 25 6 19.1 3.3 2 10f 25v 150f 35v 2 100f 6.3v 330f 6.3v none 100pf 7 120 240 30 6 13.3 3.3 2 10f 25v 150f 35v 1 100f 6.3v 470f 4v none 100pf 7 110 214 30 6 13.3 3.3 2 10f 25v 150f 35v 3 22f 6.3v 470f 4v none 100pf 7 110 214 30 6 13.3 3.3 2 10f 25v 150f 35v 4 100f 6.3v none none 100pf 7 114 230 30 6 13.3 3.3 2 10f 25v 150f 35v 1 100f 6.3v 470f 4v none 100pf 12 110 214 30 6 13.3 3.3 2 10f 25v 150f 35v 3 22f 6.3v 470f 4v none 150pf 12 110 214 35 6 13.3 3.3 2 10f 25v 150f 35v 2 100f 6.3v 330f 6.3v none 100pf 12 110 214 35 6 13.3 3.3 2 10f 25v 150f 35v 4 100f 6.3v none none 100pf 12 114 230 30 6 13.3 5 2 10f 25v 150f 35v 4 100f 6.3v none none 22pf 15 188 375 25 6 8.25 5 2 10f 25v 150f 35v 4 100f 6.3v none none 22pf 20 159 320 25 6 8.25 a pplica t ions i n f or m a t ion
ltm4601a/ltm4601a-1 19 4601afc table 3. 1.5v output at 12a derating curve v in (v) power loss curve air flow (lfm) heat sink ja (c/w) lga ja (c/w) bga figures 9, 11 5, 12 figure 7 0 none 15.2 15.7 figures 9, 11 5, 12 figure 7 200 none 14 14.5 figures 9, 11 5, 12 figure 7 400 none 12 12.5 figures 10, 12 5, 12 figure 7 0 bga heat sink 13.9 14.4 figures 10, 12 5, 12 figure 7 200 bga heat sink 11.3 11.8 figures 10, 12 5, 12 figure 7 400 bga heat sink 10.25 10.75 table 4. 3.3v output at 12a derating curve v in (v) power loss curve air flow (lfm) heat sink ja (c/w) lga ja (c/w) bga figure 13 12 figure 8 0 none 15.2 15.7 figure 13 12 figure 8 200 none 14.6 15.0 figure 13 12 figure 8 400 none 13.4 13.9 figure 14 12 figure 8 0 bga heat sink 13.9 14.4 figure 14 12 figure 8 200 bga heat sink 11.1 11.6 figure 14 12 figure 8 400 bga heat sink 10.5 11 heat sink manufacturer aavid thermalloy part no: 375424b00034g phone: 603-224-9988 applica t ions in f or m a t ion
ltm4601a/ltm4601a-1 20 4601afc layout checklist/example the high integration of ltm4601a makes the pcb board layout very simple and easy. however, to optimize its electrical and thermal performance, some layout consid - erations are still necessary. ? use large pcb copper areas for high current path, in - cluding v in , pgnd and v out . it helps to minimize the pcb conduction loss and thermal stress. ? place high frequency ceramic input and output capaci - tors next to the v in , pgnd and v out pins to minimize high frequency noise. ? place a dedicated power ground layer underneath the unit. refer frequency synchronization source to power ground. ? to minimize the via conduction loss and reduce module thermal stress, use multiple vias for interconnection between top layer and other power layers. ? do not put vias directly on pads unless they are capped. ? use a separated sgnd ground copper area for com - ponents connected to signal pins. connect the sgnd to pgnd underneath the unit. figure 15 gives a good example of the recommended layout. frequency adjustment the ltm4601a is designed to typically operate at 850khz across most input conditions. the f set pin is normally left open. the switching frequency has been optimized for maintaining constant output ripple noise over most operating ranges. the 850khz switching frequency and the 400ns minimum off-time can limit operation at higher duty cycles like 5v to 3.3v, and produce excessive induc - tor ripple currents for lower duty cycle applications like 20v to 5v. the 5v out and 3.3v out drop out curves are modified by adding an external resistor on the f set pin to allow for lower input voltage operation, or higher input voltage operation. figure 15. recommended layout (lga and bga pcb layouts are identical with the exception of circle pads for bga, see package description.) a pplica t ions i n f or m a t ion signal gnd control control control 4601a f15 v out v in pgnd c out c out c in c in
ltm4601a/ltm4601a-1 21 4601afc example for 5v output ltm4601a minimum on-time = 100ns t on = ((v out ? 10pf)/i fset ), for v out > 4.8v use 4.8v ltm4601a minimum off-time = 400ns t off = t C t on , where t = 1/frequency duty cycle = t on /t or v out /v in equations for setting frequency: i fset = (v in /(3 ? r fset )), for 20v operation, i fset = 170a, t on = ((4.8 ? 10pf)/i fset ), t on = 282ns, where the internal r fset is 39.2k. frequency = (v out /(v in ? t on )) = (5v/(20 ? 282ns)) 886khz. the inductor ripple current begins to get high at the higher input voltages due to a larger voltage across the inductor. this is noted in the induc - tor ripple current vs duty cycle graph (figure 3) where i l 10a at 25% duty cycle. the inductor ripple current can be lowered at the higher input voltages by adding an external resistor from f set to ground to increase the switch- ing frequency. an 8a ripple current is chosen, and the total peak current is equal to 1/2 of the 8a ripple current plus the output current. the 5v output current is limited to 8a, so the total peak current is less than 12a. this is below the 14a peak specified value. a 100k resistor is placed from f set to ground, and the parallel combination of 100k and 39.2k equates to 28k. the i fset calculation with 28k and 20v input voltage equals 238a. this equates to a t on of 200ns. this will increase the switching frequency from ~886khz to ~1.25mhz for the 20v to 5v conversion. the minimum on-time is above 100ns at 20v input. since the switching frequency is approximately constant over input and output conditions, then the lower input voltage range is limited to 10v for the 1.25mhz operation due to the 400ns minimum off-time. equation: t on = (v out /v in ) ? (1/frequency) equates to a 400ns on-time, and a 400ns off-time. the v in to v out step-down ratio curve reflects an operating range of 10v to 20v for 1.25mhz operation with a 100k resistor to ground, and an 8v to 16v operation for f set floating. these modifications are made to provide wider input voltage ranges for the 5v output designs while limiting the inductor ripple current, and maintaining the 400ns minimum off-time. example for 3.3v output ltm4601a minimum on-time = 100ns t on = ((v out ? 10pf)/i fset ) ltm4601a minimum off-time = 400ns t off = t C t on , where t = 1/frequency duty cycle (dc) = t on /t or v out /v in equations for setting frequency: i fset = (v in /(3 ? r fset )), for 20v operation, i fset = 170a, t on = ((3.3 ? 10pf)/i fset ), t on = 195ns, where the internal r fset is 39.2k. frequency = (v out /(v in ? t on )) = (3.3v/(20 ? 195ns)) 846khz. the minimum on-time and minimum off-time are within specification at 195ns and 980ns. the 4.5v minimum input for converting 3.3v output will not meet the minimum off-time specification of 400ns. t on = 868ns, frequency = 850khz, t off = 315ns. solution lower the switching frequency at lower input voltages to allow for higher duty cycles, and meet the 400ns minimum off-time at 4.5v input voltage. the off-time should be about 500ns, which includes a 100ns guard band. the duty cycle for (3.3v/4.5v) 73%. frequency = (1 C dc)/t off , or (1 C 0.73)/500ns = 540khz. the switching frequency needs to be lowered to 540khz at 4.5v input. t on = dc/frequency, or 1.35s. the f set pin voltage is 1/3 of v in , and the i fset current equates to 38a with the internal 39.2k. the i fset current needs to be 24a for 540khz operation. a resis- tor can be placed from v out to f set to lower the effective i fset current out of the f set pin to 24a. the f set pin is 4.5v/3 =1.5v and v out = 3.3v, therefore 130k will source 14a into the f set node and lower the i fset current to 24a. this enables the 540khz operation and the 4.5v to 20v input operation for down converting to 3.3v output. the frequency will scale from 540khz to 1.1mhz over this input range. this provides for an effective output current of 8a over the input range. applica t ions in f or m a t ion
ltm4601a/ltm4601a-1 22 4601afc figure 16. 5v at 8a design without differential amplifier a pplica t ions i n f or m a t ion v out v fb marg0 marg1 v out_lcl nc3 nc1 nc2 pgood mpgm run comp intv cc drv cc track/ss pllin ltm4601a-1 r1 392k 1% r fset 100k r set 8.25k c3 100f 6.3v sanyo poscap 4601a f16 v out 5v 8a track/ss control review temperature derating curve c6 100pf refer to table 2 c2 10f 25v improve efficiency for 12v input c1 10f 25v r4 100k r2 100k v in v out f set pgnd margin control sgnd 5% margin v in 10v to 20v cmssh-3c sot-323 + figure 17. 3.3v at 10a design v out v fb marg0 marg1 v out_lcl diffv out v osns + v osns ? pgood mpgm run comp intv cc drv cc track/ss pllin ltm4601a r1 392k r4 100k r2 100k r set 13.3k r fset 130k margin control c3 100f 6.3v sanyo poscap 4601a f17 v out 3.3v 10a track/ss control c6 100pf c2 10f 25v 3 v in v out f set pgnd sgnd 5% margin v in 4.5v to 16v review temperature derating curve + pgood
ltm4601a/ltm4601a-1 23 4601afc figure 19. 2-phase parallel, 1.5v at 24a design a pplica t ions i n f or m a t ion figure 18. typical 4.5v to 20v, 1.5v at 12a design v out v fb marg0 marg1 v out_lcl diffv out v osns + v osns ? pgood mpgm run comp intv cc drv cc track/ss pllin ltm4601a r1 392k 392k r4 100k r2 100k v out r set 20k c3 22f 6.3v c4 470f 6.3v v out 1.5v 24a clock sync 0 phase clock sync 180 phase c6 220pf margin control track/ss control track/ss control refer to table 2 refer to table 2 c5* 100f 25v c1 0.1f c2 10f 25v 2 v in f set pgnd sgnd v out v fb marg0 marg1 v out_lcl nc3 nc2 nc1 pgood mpgm run comp intv cc drv cc track/ss pllin ltm4601a-1 v in f set pgnd sgnd 5% margin ltc6908-1 v in 4.5v to 20v 4.5v to 20v pgood 2-phase oscillator 100pf c3 22f 6.3v 4601a f19 c7 0.033f c8 10f 25v 2 *c5 optional to reduce any lc ringing. not needed for low inductance plane connection + c4 470f 6.3v + + v + gnd set 6 5 4 1 2 3 out1 out2 mod v out = 0.6v r set 60.4k n + r set n = number of phases 118k 1% v out v fb marg0 marg1 v out_lcl diffv out v osns + v osns ? pgood mpgm run comp intv cc drv cc track/ss pllin ltm4601a r1 392k r4 100k r2 100k r set 40.2k c out1 100f 6.3v c5 0.01f c out2 470f 6.3v margin control 4601a f18 v out 1.5v 12a clock sync c3 100pf refer to table 2 for different output voltage c in bulk opt c in 10f 25v 3 cer v in v out f set pgnd sgnd 5% margin v in 4.5v to 20v review temperature derating curve + + pgood on/off
ltm4601a/ltm4601a-1 24 4601afc 4-phase, four outputs (3.3v, 2.5v, 1.8v and 1.5v) with coincident tracking typical a pplica t ions v out v fb marg0 marg1 v out_lcl diffv out v osns + v osns ? pgood mpgm run comp intv cc drv cc track/ss pllin ltm4601a r9 392k r11 100k r10 100k r18 19.1k c16 22f 6.3v c14 10f 25v 3 3.3v 2.5v at 12a r23 60.4k c15 470f 6.3v margin control clock sync 2 c18 100pf refer to table 2 v in f set pgnd sgnd 5% margin + pgood 8v to 16v on/off v out v fb marg0 marg1 v out_lcl diffv out v osns + v osns ? pgood mpgm run comp intv cc drv cc track/ss pllin ltm4601a r14 392k r16 100k r15 100k r13 40.2k c16 22f 6.3v c14 10f 25v 3 3.3v r25 60.4k c15 470f 6.3v margin control 1.5v at 12a clock sync 4 c24 100pf refer to table 2 v in f set pgnd sgnd 5% margin 4601a ta04 + pgood 8v to 16v on/off v out v fb marg0 marg1 v out_lcl diffv out v osns + v osns ? pgood mpgm run comp intv cc drv cc track/ss pllin ltm4601a r1 392k r3 100k r2 100k r12 30.1k c3 22f 6.3v c2 10f 25v 3 3.3v r21 60.4k r19 30.1k c4 470f 6.3v margin control 1.8v at 12a clock sync 3 c8 100pf refer to table 2 v in f set pgnd sgnd 5% margin + pgood 8v to 16v on/off r17 59k c26 0.1f ltc6902 4-phase oscillator 3.3v at 10a v + div ph out1 out2 set mod gnd out4 out3 v out v fb marg0 marg1 v out_lcl diffv out v osns + v osns ? pgood mpgm run comp intv cc drv cc track/ss pllin ltm4601a r27 392k r7 100k r6 100k r8 13.3k c9 22f 6.3v c7 0.15f c8 10f 25v 3 c11 100f 35v opt c10 470f 6.3v margin control track/ss control clock sync 1 c12 100pf refer to table 2 v in 3.3v f set pgnd sgnd 5% margin + pgood 8v to 16v 8v to 16v on/off + intermediate bus ?48v input r24 19.1k r26 40.2k 3.3v 3.3v 3.3v
ltm4601a/ltm4601a-1 25 4601afc bga package 133-lead (15mm 15mm 3.42mm) (reference ltm dwg # 05-08-1877 rev b) p ackage descrip t ion please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. notes: 1. dimensioning and tolerancing per asme y14.5m-1994 2. all dimensions are in millimeters ball designation per jesd ms-028 and jep95 5. primary datum -z- is seating plane 4 3 details of pin #1 identifier are optional, but must be located within the zone indicated. the pin #1 identifier may be either a mold or marked feature package top view 4 pin ?a1? corner x y aaa z aaa z package bottom view pin 1 3 see notes suggested pcb layout top view bga 133 0511 rev b ltmxxxxxx module tray pin 1 bevel package in tray loading orientation component pin ?a1? detail a 0.0000 0.0000 detail a ?b (133 places) detail b substrate 0.27 ? 0.37 2.45 ? 2.55 // bbb z d a a1 b1 ccc z detail b package side view mold cap z m x yzddd m zeee 0.630 0.025 ? 133x symbol a a1 a2 b b1 d e e f g aaa bbb ccc ddd eee min 3.22 0.50 2.72 0.60 0.60 nom 3.42 0.60 2.82 0.75 0.63 15.0 15.0 1.27 13.97 13.97 max 3.62 0.70 2.92 0.90 0.66 0.15 0.10 0.20 0.30 0.15 notes dimensions total number of balls: 133 e b e e b a2 f g bga package 133-lead (15mm 15mm 3.42mm) (reference ltc dwg # 05-08-1877 rev b) 0.6350 0.6350 1.9050 1.9050 3.1750 3.1750 4.4450 4.4450 5.7150 5.7150 6.9850 6.9850 6.9850 5.7150 5.7150 4.4450 4.4450 3.1750 3.1750 1.9050 1.9050 0.6350 0.6350 6.9850 fgh m l jk e abcd 2 1 4 3 5 6 7 12 8 9 10 11
ltm4601a/ltm4601a-1 26 4601afc lga package 133-lead (15mm 15mm 2.82mm) (reference ltm dwg # 05-08-1755, rev ?) p ackage descrip t ion notes: 1. dimensioning and tolerancing per asme y14.5m-1994 2. all dimensions are in millimeters land designation per jesd mo-222, spp-010 5. primary datum -z- is seating plane 6. the total number of pads: 133 4 3 details of pad #1 identifier are optional, but must be located within the zone indicated. the pad #1 identifier may be either a mold or marked feature symbol aaa bbb eee tolerance 0.10 0.10 0.05 2.72 ? 2.92 detail b detail b substrate mold cap 0.27 ? 0.37 2.45 ? 2.55 bbb z z 15 bsc package top view 15 bsc 4 pad 1 corner x y aaa z aaa z detail a 13.97 bsc 1.27 bsc 13.97 bsc 0.12 ? 0.28 l k j h g f e d c b package bottom view c(0.30) pad 1 3 pads see notes m a 1 2 3 4 5 6 7 8 10 9 11 12 detail a 0.630 0.025 sq. 133x s yxeee suggested pcb layout top view 0.0000 0.6350 0.6350 1.9050 1.9050 3.1750 3.1750 4.4450 4.4450 5.7150 5.7150 6.9850 6.9850 6.9850 5.7150 5.7150 4.4450 4.4450 3.1750 3.1750 1.9050 1.9050 0.6350 0.6350 0.0000 6.9850 lga 133 0807 rev ? ltmxxxxxx module tray pin 1 bevel package in tray loading orientation component pin ?a1? please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
ltm4601a/ltm4601a-1 27 4601afc pin name pin name pin name pin name pin name pin name a1 v in b1 v in c1 v in d1 pgnd e1 pgnd f1 pgnd a2 v in b2 v in c2 v in d2 pgnd e2 pgnd f2 pgnd a3 v in b3 v in c3 v in d3 pgnd e3 pgnd f3 pgnd a4 v in b4 v in c4 v in d4 pgnd e4 pgnd f4 pgnd a5 v in b5 v in c5 v in d5 pgnd e5 pgnd f5 pgnd a6 v in b6 v in c6 v in d6 pgnd e6 pgnd f6 pgnd a7 int v cc b7 pgnd c7 pgnd d7 - e7 pgnd f7 pgnd a8 pllin b8 - c8 - d8 pgnd e8 - f8 pgnd a9 track/ss b9 pgnd c9 pgnd d9 int v cc e9 pgnd f9 pgnd a10 run b10 - c10 mtp1 d10 mp t2 e10 - f10 - a11 comp b11 mpgm c11 f set d11 mpt3 e11 - f11 pgood a12 mpgm b12 f set c12 marg0 d12 marg1 e12 dr v cc f12 v fb pin name pin name pin name pin name pin name pin name g1 pgnd h1 pgnd j1 v out k1 v out l1 v out m1 v out g2 pgnd h2 pgnd j2 v out k2 v out l2 v out m2 v out g3 pgnd h3 pgnd j3 v out k3 v out l3 v out m3 v out g4 pgnd h4 pgnd j4 v out k4 v out l4 v out m4 v out g5 pgnd h5 pgnd j5 v out k5 v out l5 v out m5 v out g6 pgnd h6 pgnd j6 v out k6 v out l6 v out m6 v out g7 pgnd h7 pgnd j7 v out k7 v out l7 v out m7 v out g8 pgnd h8 pgnd j8 v out k8 v out l8 v out m8 v out g9 pgnd h9 pgnd j9 v out k9 v out l9 v out m9 v out g10 - h10 - j10 v out k10 v out l10 v out m10 v out g11 sgnd h11 sgnd j11 - k11 v out l11 v out m11 v out g12 pgood h12 sgnd j12 v osns + k12 diffv out l12 v out_lcl m12 v osns C pin assignment table 5 (arranged by pin number) package d escrip t ion
ltm4601a/ltm4601a-1 28 4601afc pin name a1 a2 a3 a4 a5 a6 v in v in v in v in v in v in b1 b2 b3 b4 b5 b6 v in v in v in v in v in v in c1 c2 c3 c4 c5 c6 v in v in v in v in v in v in pin assignment table 6 (arranged by pin function) pin name d1 d2 d3 d4 d5 d6 d8 pgnd pgnd pgnd pgnd pgnd pgnd pgnd e1 e2 e3 e4 e5 e6 e7 pgnd pgnd pgnd pgnd pgnd pgnd pgnd f1 f2 f3 f4 f5 f6 f7 f8 f9 pgnd pgnd pgnd pgnd pgnd pgnd pgnd pgnd pgnd g1 g2 g3 g4 g5 g6 g7 g8 g9 pgnd pgnd pgnd pgnd pgnd pgnd pgnd pgnd pgnd h1 h2 h3 h4 h5 h6 h7 h8 h9 pgnd pgnd pgnd pgnd pgnd pgnd pgnd pgnd pgnd pin name j1 j2 j3 j4 j5 j6 j7 j8 j9 j10 v out v out v out v out v out v out v out v out v out v out k1 k2 k3 k4 k5 k6 k7 k8 k9 k10 k11 v out v out v out v out v out v out v out v out v out v out v out l1 l2 l3 l4 l5 l6 l7 l8 l9 l10 l11 v out v out v out v out v out v out v out v out v out v out v out m1 m2 m3 m4 m5 m6 m7 m8 m9 m10 m11 v out v out v out v out v out v out v out v out v out v out v out pin name a7 a8 a9 a10 a11 a12 intv cc pllin track/ss run comp mpgm b12 f set c12 marg0 d12 marg1 e12 drv cc f12 v fb g12 pgood h12 sgnd j12 v osns + k12 diffv out l12 v out_lcl m12 v osns C pin name b7 b8 b9 b10 b11 pgnd - pgnd - mpgm c7 c8 c9 c10 c11 pgnd - pgnd mtp1 f set d7 d8 d9 d10 d11 - pgnd intv cc mtp2 mtp3 e8 e9 e10 e11 - pgnd - - f10 f11 - pgood g10 g11 - sgnd h10 h11 - sgnd j11 - p ackage descrip t ion
ltm4601a/ltm4601a-1 29 4601afc information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa - tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. r evision h is t ory rev date description page number c 8/11 added bga package. changes reflected throughout the data sheet. 1 to 30 (revision history begins at rev c)
ltm4601a/ltm4601a-1 30 4601afc ? linear technology corporation 2007 lt 0811 rev c ? printed in usa linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 l fax : (408) 434-0507 l www.linear.com p ackage p ho t os part number description comments ltc2900 quad supply monitor with adjustable reset timer monitors four supplies; adjustable reset timer ltc2923 power supply tracking controller tracks both up and down; power supply sequencing lt3825/lt3837 synchronous isolated flyback controllers no opto-coupler required; 3.3v, 12a output; simple design ltm4600 10a dc/dc module regulator basic 10a dc/dc module regulator ltm4601 12a dc/dc module regulator with pll, output tracking/ margining and remote sensing synchronizable, polyphase operation to 48a, ltm4601-1 version has no remote sensing ltm4602 6a dc/dc module regulator pin compatible with the ltm4600 ltm4603 6a dc/dc module regulator with pll and output tracking/margining and remote sensing synchronizable, polyphase operation, ltm4603-1 version has no remote sensing, pin compatible with the ltm4601 ltm4604a 4a low voltage dc/dc module regulator 2.7v v in 5.5v; 0.8v v out 5v, 15mm 9mm 2.32mm (ultrathin) lga package ltm4608a 8a low voltage dc/dc module regulator 2.7v v in 5.5v; 0.6v v out 5v; 15mm 9mm 2.82mm lga package this product contains technology licensed from silicon semiconductor corporation. ? r ela t e d p ar t s 15mm 15mm 2.82mm 15mm 15mm 3.42mm

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